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PRELIMINARY CM3121 Dual Linear Voltage Regulator for DDR-I and DDR-II Memory
Features
* * * * Fully integrated power solution for DDR memory ICs Ideal for DDR-I (2.5VDDQ) and DDR-II (1.8VDDQ) Lowest system cost and smallest footprint with just two external output capacitors Two linear regulators: - VDDQ regulator with a maximum output current of 1.5A shared by DRAM and VTT regulator - source-sink VTT regulator with maximum output current of 0.5A (DDR-I) or 0.3A (DDR-II) Fault output indicates overcurrent condition in either regulator, under voltage lock-out and overtemperature condition Reverse current protection if host is powered off PSOP-8 package with integrated heat spreader Lead-free versions available
Product Description
The CM3121 provides an integrated power solution for DDR-I and DDR-II memory systems in consumer electronics applications. The CM3121 is ideal for a 2.8V to 3.6V supply for DDR-I memory and 2.2V to 2.8V for DDR-II memory. The CM3121 features two independent linear regulators for VDDQ and VTT supply regulation. The default voltage for VDDQ is 2.5V. The VDDQ regulator SENSE pin allows for setting VDDQ in the 2.2V to 2.8V range, or DDR-II memories from 1.7V to 1.9V. The VTT regulator output is always half the VDDQ voltage, derived internally. A capacitor should be connected to each of the two outputs. When EN_DDR is set high, the two DDR regulators are disabled to minimize overall system power dissipation such as when memory is in standby. The FAULT pin goes low whenever either of the two regulators goes into current limit mode, the input voltage drops too far or if overtemp occurs.
* * * *
Applications
* DDR-I and DDR-II memory power for: - Set Top Boxes, DVD Players, Games - Digital TVs, Flat Panel Displays - Printers, Digital Projectors - Embedded systems - Communications systems
The CM3121 is available in a PSOP-8 package that has excellent thermal dissipation. It is available with optional lead-free finishing. .
Typical Application Circuit
2.8V to 3.3V
Circuit Schematic
VCC
VDDQ REGULATOR
VDDQ SENSE VDDQ
VCC VDDQ REGULATOR
VDDQ SENSE VDDQ
VREF
VDDQ = 2.5V
CCC
VREF
VDDQ SENSE_ VDDQ
Enable DDR Memory #
EN_DDR
CDDQ
EN_DDR
DDR MEMORY
R R
VTT REGULATOR
VTT
R
VTT=1.25V
VTT REGULATOR
VTT
R
VTT SENSE_VTT
SENSE VTT
CTT
SENSE VTT
CURRENT LIMIT OVERTEMP LOW INPUT
FAULT
CPU CORE + I/O
CURRENT LIMIT OVERTEMP LOW INPUT
FAULT
GND
GND
(c) 2004 California Micro Devices Corp. All rights reserved. 11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
PRELIMINARY CM3121
Functional Description
The CM3121 provides power for DDR-I/DDR-II memories from two voltage regulators on-chip. There is an over-temperature thermal shutdown if any of the regulators overheat. Each regulator also has reverse current protection in the event of any being shut down. The VDDQ linear regulator can provide 2.5V/1.8V for DDR-I/-II memory at up to 1.5A. An external feedback resistor divider R1 and R2, when connected to the SENSE_VDDQ pin, enables selection of VDDQ output voltages from 2.2V to 2.8V for use with DDR-I memories requiring other than 2.5V for VDDQ (see Figure 5). In this mode, the voltage on VDDQ is detemined as follows: (R1+R2) VDDQ = 1.25V x ---------------------R2 When SENSE_VDDQ is connected to GND or left open, VDDQ is fixed at 2.50V (and VTT at 1.25V). For DDR-II operation, VDDQ can be set from 1.7V to 1.9V. The VTT regulator is a linear source-sink regulator powered from the VDDQ output that supplies the VTT supply required by DDR-I memory termination resistors. This regulator sinks or sources up to 0.5A. The VTT output voltage accurately tracks VDDQ/2 to 1%. When there is no VCC provided, VTT is powered down and its output is 0V. This regulator has overload current limiting of 0.6A minimum. The EN_DDR pin when set active low enables the CM3121 to operate in normal mode with VDDQ and VTT active. When EN_DDR is high, the CM3121 is disabled and both VDDQ and VTT are set to 0V. The FAULT output is normally at logic high but when an overcurrent occurs on either VDDQ or VTT outputs, FAULT goes active low, and remains low as long as the overcurrent fault persists. Also if the chip goes into thermal overload, or the input voltage VCC drops sufficiently that the chip goes into Under Voltage Lock-Out mode (UVLO), FAULT goes active low, and remains low as long as the condition persists.
PACKAGE / PINOUT DIAGRAM
TOP VIEW
VCC VDDQ VTT GND 1 2 3 4 8 7 6 5 SENSE_VDDQ FAULT SENSE_VTT EN_DDR
Note: This drawing is not to scale.
8-Lead PSOP
PIN DESCRIPTIONS
LEAD 1 2 3 4 5 6 7 8 PAD NAME VCC VDDQ VTT GND EN_DDR SENSE_VTT FAULT SENSE_VDDQ GND DESCRIPTION Input supply. VDDQ output. VTT output for termination resistors or VREF Ground reference. Enable DDR power. Active low input. Sense input for VTT rail adjustment. Overcurrent Fault / UVLO indication, active low output. Sense input for VDDQ rail adjustment. Tied to ground reference.
(c) 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
11/12/04
PRELIMINARY CM3121
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Leads 8 Package PSOP-8 Ordering Part Number1 CM3121-02SB Part Marking CM3121 02SB Lead-free Finish Ordering Part Number1 CM3121-02SH Part Marking CM3121 02SH
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER ESD (Human Body Model) Pin Voltages VCC EN_DDR, SENSE_VDDQ, SENSE_VTT Storage Temperature Range Operating Temperature Range Ambient Junction RATING UNITS V V V C C C
2000
[GND - 0.6] to [+6.5] [GND - 0.6] to [VCC + 0.6] -40 to +150 -40 to +85 0 to +125
STANDARD OPERATING CONDITIONS
PARAMETER Ambient Operating Temperature Range 1. VDDQ Regulator DDR-I Supply Voltage VCC DDR-II Supply Voltage VCC Load Current (note 1) CCC, CDDQ 2. VTT Regulator DDR-I Supply Voltage VDDQ DDR-II Supply Voltage VDDQ DDR-I Load Current DDR-II Load Current CTT 2.3 to 2.8 1.7 to 1.9 0 to 500 0 to 300 47 V V mA mA F [VDDQ + 0.3] to 3.6 2.2 to 2.8 0 to 1500 10, 10 V V mA F RATING -40 to +85 UNITS C
Note 1: The VDDQ regulator provides power for both the memory load and the VTT regulator, supplying a total of 1.5A to the VDDQ and VTT outputs. For example, if the VDDQ load current is 1.2A, then the maximum VTT load current will be 0.3A, regardless of the actual VTT output current rating.
(c) 2004 California Micro Devices Corp. All rights reserved. 11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
PRELIMINARY CM3121
Specifications (cont'd)
DDR-I Specifications ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL TOVER THYST ICCN ICCQ VIH VIL UVLO tRISE VCC MIN VDDQ DEF VDDQ ADJ VDDQ LD VDDQ LINE eN DDQ IDDQ LIM IDDQ SC PARAMETER Shutdown Junction Temperature Junction Temp Hysterisis Normal Mode VCC Supply Current Shutdown Mode VCC Supply Current EN_DDR Input High Threshold EN_DDR Input Low Threshold Under Voltage Lock-Out VDDQ Rise TIme Input Voltage Default Output Voltage Range Adjustable Output Voltage Range Load Regulation Line Regulation Output Noise Voltage Current Limit Short Circuit Current IC in shutdown EN_DDR = logic "0", EN_CORE =logic "0" EN_DDR = logic "1", VDDQ = 0V, VTT = 0V VCC =3.3V VCC =3.3V IDDQ = 10mA VCC = 3.3V, CDDQ = 10F VDDQ = 2.5V, IDDQ = 1.5A, SENSE_VDDQ = 0V, Note 2 IDDQ = 0.01A, 2.8V VCC 3.6V, SENSE_VDDQ = 0V, Note 2 VCC = 3.6V, SENSE_VDDQ tied to external resistors R1 and R2, Note 2 TA = 25C, VCC = 3.3V, 0.01A IDDQ 1.0A, Note 2 -1.0 49 1.7 2.0 0.5 1.0 % Vrms A A 2.8V VCC 3.6V, Note 2 BW = 10Hz - 100kHz, CDDQ = 10F Note 2 VDDQ < 0.3V 2.80 2.45 1.6 2.50 2.55 2.8 2.5 0.5 2.0 0.4 1.8 CONDITIONS General Parameters 150 25 700 2 1100 10 C C A A V V V ms
(SEE NOTE1)
MIN
TYP
MAX
UNITS
VDDQ Regulator Parameters V V V %
TA = 25C, IDDQ = 0.01A,
(c) 2004 California Micro Devices Corp. All rights reserved.
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430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
11/12/04
PRELIMINARY CM3121
ELECTRICAL OPERATING CHARACTERISTICS (CONT'D) (SEE NOTE1)
VTT Regulator Parameters VTT VTT REF VTT LD VTT LINE eN TT ITT LIM ITT SC Output Voltage Range Output Voltage Range Load Regulation Line Regulation Output Noise Voltage Current Limit Short Circuit Current VTT < 0.3V VDDQ = 2.5V, ITT = 0.01A, VDDQ = 2.500V, ITT = 0.01A TA = 25C, VDDQ = 2.5V, 0.01A ITT 0.5A TA = 25C, ITT = 0.01A, 1.20 1.225 -1.0 -1.0 1.25 1.250 51 0.6 0.8 0.3 1.30 1.275 1.0 1.0 V V % % Vrms A A
2.8V VCC 3.6V, Note 2 BW = 10Hz - 100kHz, CTT = 10F
Note 1: All parameters specified at TA = -40C to +85C unless otherwise noted. Note 2: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A. So the maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current.
DDR-II Specifications ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL TOVER THYST ICCN ICCQ VIH VIL UVLO tRISE PARAMETER Shutdown Junction Temperature Junction Temp Hysterisis Normal Mode VCC Supply Current Shutdown Mode VCC Supply Current EN_DDR Input High Threshold EN_DDR Input Low Threshold Under Voltage Lock-Out VDDQ Rise TIme IC in shutdown EN_DDR = logic "0", EN_DDR = logic "1", VDDQ = 0V, VTT = 0V VCC =3.3V VCC =3.3V IDDQ = 10mA VCC = 3.3V, CDDQ = 10F 0.5 2.0 0.4 1.8 CONDITIONS General Parameters 150 25 700 2 1100 10 C C A A V V V ms
(SEE NOTE 3)
MIN
TYP
MAX
UNITS
(c) 2004 California Micro Devices Corp. All rights reserved. 11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
PRELIMINARY CM3121
ELECTRICAL OPERATING CHARACTERISTICS (CONT'D) (SEE NOTE 3)
VDDQ Regulator Parameters VCC MIN VDDQ VDDQ ADJ VDDQ LD VDDQ LINE eN DDQ IDDQ LIM IDDQ SC VTT VTT LD VTT LINE eN TT ITT LIM ITT SC Input Voltage Default Output Voltage Range Adjustable Output Voltage Range Load Regulation Line Regulation Output Noise Voltage Current Limit Short Circuit Current VDDQ = 2.5V, IDDQ = 1.5A, SENSE_VDDQ = 0V, Note 4 IDDQ = 0.01A,VCC = 3.3V, SENSE_VDDQ = 0V, Note 4 VCC = 3.3V, SENSE_VDDQ tied to external resistors R1 and R2, Note 4 TA = 25C, VCC = 2.5V, 0.01A IDDQ 1.0A, Note 4 -1.0 49 1.7 2.0 0.5 1.0 % 2.2V VCC 2.8V, Note 4 BW = 10Hz - 100kHz, CDDQ = 10F Note 4 VDDQ < 0.3V VDDQ = 1.8V, ITT = 0.01A, TA = 25C, VDDQ = 1.8V, 0.01A ITT 0.3A 2.2V VCC 2.8V TA = 25C, ITT = 0A, BW = 10Hz - 100kHz, CTT = 10F 0.4 VTT < 0.3V 0.86 -1.0 -1.0 Vrms A A 2.2 1.75 1.6 1.80 1.85 2.8 2.5 V V V %
TA = 25C, IDDQ = 0.01A,
VTT Regulator Parameters Output Voltage Range Load Regulation Line Regulation Output Noise Voltage Current Limit Short Circuit Current 0.90 51 0.6 0.3 0.94 1.0 1.0 V % %
Vrms A A
Note 3: All parameters specified at TA = -40C to +85C unless otherwise noted. Note 4: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A. So the maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current.
VCC(1) 2.8V to 3.6V X
EN_DDR Low High
VDDQ OUT VDDQ 0V
VTT OUT VDDQ / 2 0V
Table 1: Truth Table for CM3121
(c) 2004 California Micro Devices Corp. All rights reserved.
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430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
11/12/04
PRELIMINARY CM3121
Performance Information
Power Supply Ripple Rejection CCC = 10F, VCC = 3.3V, ILOAD = 50mA, PSRR measured with 50mV pk-pk sin wave on VCC.
50 45 40 35
PSRR (dB)
30 25 20 15 10 5 0 10 100 1000 Frequency (Hz) 10000 100000
Figure 1. VDDQ PSRR (VDDQ = 2.5V)
60 50 40
PSRR (dB)
30 20 10 0 10 100 1000 Frequency (Hz) 10000 100000
Figure 2. VTT PSRR (VTT = 1.25V)
(c) 2004 California Micro Devices Corp. All rights reserved. 11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
7
PRELIMINARY CM3121
Performance Information (cont'd)
Typical Thermal Characteristics The overall junction to ambient thermal resistance (JA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (JC) which is defined by the package style, and the second path is case to ambient (CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TAMB + PD ( JC ) + PD ( CA ) = TAMB + PD ( JA) When a CM3121-02SB/SH (PSOP-8) is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the resulting JA is 40C/W. Based on the over temperature limit of 150 C with an ambient of 70C, the available power of this package will be: 150 C - 70 C PD = -------------------------------------- = 2W 40 C/ W PCB Layout Considerations The CM3121-02SB/SH has a heat spreader attached to the bottom of the PSOP-8 package in order for heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq in. of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and not near other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3121 package to ambient, JA, of around 40C/W.
Figure 3. Recommended Heat Sink PCB Layout
(c) 2004 California Micro Devices Corp. All rights reserved.
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430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
11/12/04
PRELIMINARY CM3121
Application Information
Other Applications The CM3121 can be used without any external resistors if a VDDQ voltage of 2.5V is required by connecting the SENSE_VDDQ pin to GND. Also in applications where a reference voltage (VREF) is required, a PCB trace directly from the VTT pin can be used. The VTT output pin has an error relative to VDDQ/2 of up to +/-25mV, which is well within most DDR system specs of +/-50mV. This is because the VTT output internally tracks the VDDQ output very closely due to the matched on-chip resistors R that tap down from the VDDQ rail, and the low offset voltage of the VTT regulator. It is recommended that the VREF trace be connected directly to the VTT pin, to eliminate noise and ripple on the VTT line caused by current switching .
2.8V to 3.6V CCC
VCC VDDQ REGULATOR
VDDQ SENSE VDDQ
VREF
Enable DDR Memory #
EN_DDR
CDDQ
DDR MEMORY
R R VTT REGULATOR
VTT
VREF=1.25V VTT=1.25V
SENSE VTT
CTT
CURRENT LIMIT OVERTEMP LOW INPUT
FAULT
CPU CORE + I/O
GND
Figure 4. Typical Application for the CM3121
(c) 2004 California Micro Devices Corp. All rights reserved. 11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
9
PRELIMINARY CM3121
Application Information (cont'd)
DDR-II Application For DDR-II applications, it is recommended that a lower input voltage than 3.3V be applied to reduce overall power dissipation. The input voltage can be as low as 2.1V worst case, so an input voltage of 2.4V 10% would be the best input voltage for the least power dissipation. Also to obtain a VDDQ voltage of 1.8V, a resistor divider comprising R1 = 56K and R2 = 130K would result in an output voltage of 1.79V for VDDQ, and a VTT of 0.895V. The maximum current IDDQ for the CM3121 in a DDRII application is 1.5V, and the maximum for ITT is 0.3V. This should be satisfactory for most DDR- II applications because the DDR- II memories do not require a VTT, so the only current needed is for either a reference voltage or a controller input. .
2.15V to 3.6V CCC
VCC VDDQ REGULATOR
VDDQ SENSE VDDQ
* VDDQ = 1.25V x
R1 + R2 --------------------R2
VDDQ=1.8V* R1 R2 R R VTT REGULATOR
VTT
VREF
Enable DDR Memory #
EN_DDR
CDDQ
DDR MEMORY
VTT=0.90V
SENSE VTT
CTT
CURRENT LIMIT OVERTEMP LOW INPUT
FAULT
CPU CORE + I/O
GND
Figure 5. Minimal CM3132 DDR-II power solution.
(c) 2004 California Micro Devices Corp. All rights reserved.
10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
11/12/04
PRELIMINARY CM3121
Mechanical Details
PSOP-8 Mechanical Specifications Dimensions for CM3121 devices packaged in an 8lead PSOP package with a heatspreader are shown below. Mechanical Package Diagrams
TOP VIEW
PACKAGE DIMENSIONS
Package Leads Dimensions A A1 B C D E e H L x** y** # per tube # per tape and reel Millimeters Min 1.30 0.03 0.33 0.18 4.83 3.81 1.02 5.79 0.41 3.30 2.29 Max 1.62 0.10 0.51 0.25 5.00 3.99 1.52 6.20 1.27 3.81 2.79 Min 0.051 0.001 0.013 0.007 0.190 0.150 0.040 0.228 0.016 0.130 0.090 PSOP-8 8 Inches Max 0.064 0.004 0.020 0.010 0.197 0.157 0.060 0.244 0.050 0.150 0.110
D
8 7 6 5
H
Pin 1 Marking
E
1
2
3
4
BOTTOM VIEW
D
1 2 3 4 Heat Slug
x Hy
x/2
E
y/2
100 pieces* 2500 pieces Controlling dimension: inches
8 7 6 5
* This is an approximate number which may vary.
SIDE VIEW
** Centered on package centerline.
A
SEATING PLANE
A1 B e
END VIEW
C
L
Package Dimensions for PSOP-8
(c) 2004 California Micro Devices Corp. All rights reserved. 11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
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